Method and system for implementing pattern matching of integrated circuit features using voronoi diagrams
US8122407B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 12, 2008 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Aug 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F18/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for implementing pattern matching of integrated circuit features includes computing Voronoi edge regions for both a reference configuration and a search space of an integrated circuit design to be searched and presenting the computed Voronoi edge regions of the reference configuration to a user; receiving one or more selected bisectors of the Voronoi computed reference configuration from the user, indicative of user identified salient regions of design shapes and/or corners to be searched, so as to define one or more search elements, wherein a search element comprises a given bisector and a pair of Voronoi edge regions bounded thereby; constructing a search pattern from the one or more search elements defined from the reference configuration; examining the search space for matching sequences with respect to the search pattern; and highlighting resulting matching patterns in the search space for the user.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.