Balancing of load in a network processor
US8122455B2 · kind B2 · utility
6Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2007 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Dec 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5083
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to an aspect of the present invention, a scheduler balances the load on the microengines comprising one or more threads allocated to execute a corresponding microblock. The scheduler determines the load on each microengine at regular time intervals. The scheduler balances the load of a heavily loaded microengine by distributing the corresponding load among one or more lightly loaded microengines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.