Local bottom gates for graphene and carbon nanotube devices
US8124463B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2009 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Jan 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K85/221
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.