Method to enhance channel stress in CMOS processes
US8124486B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2011 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Aug 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.