Non-volatile memory devices with charge storage regions
US8125020B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2007 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Sep 24, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias to the control gate directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.