Embedded scribe lane crack arrest structure for improved IC package reliability of plastic flip chip devices
US8125053B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2009 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Feb 4, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system, method, and apparatus for suppressing cracks in the wafer dicing process. A wafer includes a plurality of die attached to a frame and mounting tape, with the die separated by a plurality of scribe lanes. An existing die seal generally protects the boundary of the die but can still fail to fully protect the die from excessive cracks induced by dicing damage, particularly when dicing through brittle, low-k dielectrics. The system, method, and apparatus includes embedding a crack arrest structure (CAS) between adjacent scribe lanes. Upon a mechanical saw dicing the wafer, the CAS creates a moisture diffusion block, and can absorb or significantly diminish the energy of cracks propagating towards the individual die seals. Furthermore, the system, method, and apparatus can be implemented without the need to increase the width of the scribe lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.