PLL circuit
US8125255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2011 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Feb 22, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/0328
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.