Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation
US8125267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2010 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Sep 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.