Processing pipeline with latency bypass
US8125489B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2006 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Oct 16, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing pipeline employs one or more bypass caches to allow a transaction that is dependent on the results of a prior transaction to be processed before the prior transaction has completed processing. Each bypass cache is coupled to the input and the output of one of the sections of the processing pipeline so that results of a transaction from that section can be written into or read from the bypass cache as soon as that transaction has been completely processed through that section. With such a configuration, more transactions can be processed by the processing pipeline in a shorter amount of time. This is especially true for very deep pipelines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.