Semiconductor memory device
US8125820B2 · kind B2 · utility
2Cited by
1References
28Claims
0Family size
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Key dates
| Filing date | Sep 13, 2010 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Sep 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory to which a bit line potential step-down technique is applied is provided. The memory includes an IO block including first transistors which control potentials of first bit lines provided with respect to columns of memory cells, and first logic gates which control the first transistors. The drain or source of each first transistor is connected to an input of the corresponding first logic gate, and the gate of each first transistor is connected to an output of the corresponding first logic gate. The first transistors are driven by pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.