Semiconductor integrated circuit device and operating method thereof
US8125845B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2010 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Aug 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.