Circuit and method for on-chip jitter measurement
US8126041B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 19, 2007 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Nov 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.