Unlimited sub-segment support in a buffer manager
US8127100B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2008 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Jul 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0871
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of buffer management may employ a common data structure that is recognizable by both hardware and firmware. In some implementations, hardware register settings may be programmed independent of firmware updates to an internal sub-segment description table maintained in an ASIC or other buffer manager logic. Implementation of such a common data structure in external memory may substantially reduce hardware real estate and complexity of a buffer manager ASIC by minimizing the number of required registers and eliminating the need for an internal sub-segment descriptor table. In addition, by eliminating the internal sub-segment descriptor table and allowing buffer manager logic to recognize a common data structure in external memory, the number of buffer sub-segments recognized by the buffer manager may be readily expanded, and may be limited only by the size of the external memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.