SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream
US8127112B2 · kind B2 · utility
12Cited by
94References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2010 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Dec 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/742
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.