System and method for executing instructions prior to an execution stage in a processor
US8127114B2 · kind B2 · utility
1Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2007 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Mar 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of processing a plurality of instructions in multiple pipeline stages within a pipeline processor is disclosed. The method partially or wholly executes a stalled instruction in a pipeline stage that has a function other than instruction execution prior to the execution stage within the processor. Partially or wholly executing the instruction prior to the execution stage in the pipeline speeds up the execution of the instruction and allows the processor to more effectively utilize its resources, thus increasing the processor's efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.