Hardware warning protocol for processing units
US8127181B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2007 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Oct 12, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/366
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing units are configured to capture the unit state in unit level error status registers when a runtime error event is detected in order to facilitate debugging of runtime errors. The reporting of warnings may be disabled or enabled to selectively monitor each processing unit. Warnings for each processing unit are propagated to an exception register in a front end monitoring unit. The warnings are then aggregated and propagated to an interrupt register in a front end monitoring unit in order to selectively generate an interrupt and facilitate debugging. A debugging application may be used to query the interrupt, exception, and unit level error status registers to determine the cause of the error. A default error handling behavior that overrides error conditions may be used in conjunction with the hardware warning protocol to allow the processing units to continue operating and facilitate in the debug of runtime errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.