System and method including built-in self test (BIST) circuit to test cache memory
US8127184B2 · kind B2 · utility
8Cited by
22References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 26, 2008 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Jun 12, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resizable cache memory and a system including a Built-In Self Test (BIST) circuit configured to test a cache memory are disclosed. The system further includes a non-volatile storage device including an E-fuse array to store one or more indicators. Each indicator identifies a corresponding memory address of a failed location of the cache memory that has been detected by the BIST circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.