SDRAM convolutional interleaver with two paths
US8127199B2 · kind B2 · utility
6Cited by
9References
17Claims
0Family size
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Key dates
| Filing date | Apr 13, 2007 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Dec 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An SDRAM convolutional interleaver with two paths. Symbols are assigned to a given one of the two paths, then are sorted to minimize (to one) a number of breaks in a sequential Interleaver write address. After sorting, the symbols are stored staggered in SRAM and burst written to SDRAM. Before writing to SDRAM, data is accumulated for four symbols at a time, and the data is written four symbols wide to optimize SDRAM access time. 8 bit symbols are written 32 bits at a time to SDRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.