Error correction code generation method and memory control device
US8127205B2 · kind B2 · utility
8Cited by
5References
8Claims
0Family size
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Key dates
| Filing date | Sep 28, 2007 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | Dec 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in a register, the store data is written to the cache memory, the stored contents of the register are merged with the store data, and an error correction code is generated for a result of the merger.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.