Semiconductor integrated device and manufacturing method for the same
US8129793B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2008 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Dec 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first exemplary aspect of an exemplary embodiment of the present invention is a semiconductor integrated device comprising a semiconductor substrate, a first impurity layer of a first conductivity type formed in the semiconductor substrate, a second impurity layer of a second conductivity type formed on the first impurity layer, a first well of the first conductivity type formed on the second impurity layer and supplied with potential from the first impurity layer via an impurity region of the first conductivity type selectively formed in a part of the second impurity layer, and a second well of the second conductivity type formed on the second impurity layer and supplied with potential from the second impurity layer, wherein the impurity concentrations of the first impurity layer and the impurity region are higher than that of the first well, and the impurity concentration of the second impurity layer is higher than that of the second well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.