Interfacing between differing voltage level requirements in an integrated circuit system
US8130030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Oct 31, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.