Methods and devices for leakage current reduction
US8130042B2 · kind B2 · utility
9Cited by
13References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2010 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Jul 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and devices for leakage current reduction are described. A regulator transistor is connected to a switch to bias the transistor with a first voltage during an ON state and a second voltage during the OFF state of the transistor. The switchable bias allows leakage current decrease and “on” resistance increase of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.