Method and system for varactor linearization
US8130051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2008 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Dec 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01G7/06
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Aspects of a method and system for varactor linearization are provided. In this regard, a relationship between control voltage and capacitance of a variable capacitor may be controlled utilizing a plurality of bias voltages communicatively coupled to a corresponding plurality of bias terminals of said variable capacitor. The variable capacitor may comprise a plurality of two-terminal unit varactors and a first terminal of each unit varactor may be coupled to an RF terminal of the variable capacitor, a second terminal of one of the unit varactors may be coupled to the control voltage, and a second terminal of each of the remaining unit varactors may be coupled to one of the bias voltages. The bias voltages may be generated via a resistor ladder and/or via the resistive nature of a portion of semiconductor substrate. The bias voltages may linearize the relationship between the control voltage and the capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.