Discrete-time delta-sigma modulator with improved anti-aliasing at lower quantization rates
US8130127B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2010 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Sep 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/452
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A discrete time delta-sigma modulator circuit, which may be used to implement an analog-to-digital converter (ADC) provides improved anti-aliasing performance when lower quantization rates are selected, by maintaining the clocking rate of a first stage in the delta-sigma modulator loop filter at a rate higher than would ordinarily be selected for a lower quantization rate. To accomplish the anti-aliasing improvement, the ratio between the quantization rate and the clocking rate of the first integrator is reduced at the lower quantization rate, resulting in a first true alias image at a multiple of the quantization rate, permitting anti-aliasing filters to more effectively attenuate the alias image, and attenuating the images spaced at the quantization rate via the averaging operation of the first integrator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.