Digital power factor correction
US8130522B2 · kind B2 · utility
35Cited by
2References
26Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 30, 2008 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | May 17, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A digital PFC (DPFC) control approach that requires no input voltage sensing or current loop compensation is described. The approach can provide stable, low-harmonic operation over a universal input voltage range and load ranging from high-load operation in continuous conduction mode down to near-zero load. A fast voltage loop can also be incorporated into a DPFC controller to provide additional control of the power stage. A controller can be based on low-resolution DPWM and A/D converters, can be implemented without microcontroller or DSP programming, and is well suited for simple, low-cost integrated-circuit realizations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.