Memory device and method of operation thereof
US8130579B2 · kind B2 · utility
11Cited by
2References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 3, 2010 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Aug 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices and methods of operating a memory cell are disclosed in which a bitline can be grounded after charge sharing with an electrically floating ground line and before writing data to the memory cell. An electric potential of an upper power supply node of a memory cell can be lowered and an electric potential of a lower power supply node of the memory cell can be raised before writing data to the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.