Systems and methods for intelligent probe testing
US8130661B2 · kind B2 · utility
11Cited by
10References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 2, 2004 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Mar 1, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/55
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods are disclosed for testing a processor having at least a first interface. In one embodiment, the method includes configuring, at the processor, a second interface, such that the configured second interface has one or more quality of service parameters representative of the first interface; sending one or more packets through the configured second interface, the one or more packets being representative of another packet received at the first interface; and determining, based on the one or more packets, one or more performance parameters corresponding to the first interface under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.