On-chip and chip-to-chip routing using a processor element/router combination
US8130754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Jul 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is shown for on-chip and chip-to-chip routing. The system and method includes a processor element residing on a processor die to process a data packet received at the processor die. The system and method also include a router residing on the process die to route the data packet received at the processor die. Further, the system and method includes a switch core residing on the processor die to switch a communication channel along which the data packet is to be transmitted. Additionally, the system and method includes a switch core to identify a destination processing element and router (PE/R) module for a data packet, the switch core and the destination PE/R module residing on a common processor die. Moreover, the system and method includes a communication channel to operatively connect the switch core and the destination PE/R module on the common processor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.