Link layer device with clock processing hardware resources shared among multiple ingress and egress links
US8130777B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2006 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Aug 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a communication system comprising a link layer device connectable to one or more physical layer devices, the link layer device is configured using an efficient shared architecture for processing data associated with a plurality of links including at least one ingress link and at least one egress link. The link layer device comprises an ingress data clock processor configured to generate an ingress clock signal for processing data associated with said at least one ingress link, an egress data clock processor configured to generate an egress clock signal for processing data associated with said at least one egress link, and a control and configuration unit shared by the ingress data clock processor and the egress data clock processor. Another aspect of the invention relates to a buffer adaptive processor that in an illustrative embodiment limits clock variability in the presence of cell delay variation or cell loss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.