Calibrating a phase detector and analog-to-digital converter offset and gain
US8130888B2 · kind B2 · utility
4Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Jan 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0004
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.