Constructing variability maps by correlating off-state leakage emission images to layout information
US8131056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2008 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Sep 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Improved techniques are disclosed for monitoring or sensing process variations in integrated circuit designs. Such techniques provide such improvements by constructing variability maps correlating leakage emission images to layout information. By way of example, a method for monitoring one or more manufacturing process variations associated with a device under test (e.g., integrated circuit) comprises the following steps. An emission image representing an energy emission associated with a leakage current of the device under test is obtained. The emission image is correlated with a layout of the device under test to form a cross emission image. Common structures on the cross emission image are selected and identified as regions of interest. One or more variability measures (e.g., figures of merit) are calculated based on the energy emissions associated with the regions of interest. A variability map is created based on the calculated variability measures, wherein the variability map is useable to monitor the one or more manufacturing process variations associated with the device under test.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.