Bus signal control circuit for detecting bus signal abnormalities using separate bus diagnosis line
US8131900B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | May 6, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0745
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.