System and method of signal processing engines with programmable logic fabric
US8131909B1 · kind B1 · utility
2Cited by
26References
18Claims
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Key dates
| Filing date | Sep 19, 2007 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | May 23, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.