Method and apparatus for implementing a combined data/coherency cache
US8131936B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2005 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Feb 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for implementing a combined data/coherency cache for a shared memory multi-processor. The combined data/coherency cache includes a system cache with a number of entries. The method includes building a system cache directory with a number of entries equal to the number of entries of the system cache. The building includes designating a number of sub-entries for each entry which is determined by a number of sub-entries operable for performing system cache coherency functions. The building also includes providing a sub-entry logic designator for each entry, and mapping one of the sub-entries for each entry to the system cache via the sub-entry logic designator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.