Memory access control device equipped with memory access request generating modules/arbitrator and control method thereof
US8131949B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 23, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Oct 14, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory access control apparatus includes a plurality of memory access request generating modules and an arbitrator. When one of the memory access request generating modules receives a second memory access event while a memory device is performing a first memory access operation according to a first memory access request in response to a first memory access event, the memory access request generating module outputs a second memory access request corresponding to the second memory access event to the memory device after a delay time. The arbitrator is implemented for arbitrating memory access requests respectively outputted from the memory accessing request generating modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.