Semiconductor memory device having processor reset function and reset control method thereof
US8131985B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2008 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Jan 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.