Nonvolatile semiconductor memory device and manufacturing method thereof
US8133782B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2011 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Feb 16, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.