Semiconductor device having a wafer level chip size package structure
US8134238B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 2010 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a wafer level chip size package may include a semiconductor substrate having an integrated circuit formed thereon; a plurality of electrode pads formed on the semiconductor substrate; at least one rewiring layer which may include rewiring formed adjacent to the plurality of electrode pads; and a plurality of external electrodes formed on the rewiring layer. The plurality of electrodes and plurality of external electrodes may be sectioned and arranged in four areas having the same shapes. Each area may include a first group of N number of external electrodes arranged along an edge of the semiconductor substrate, a second group of (N-2) number of external electrodes arranged inside the first group of external electrodes, and a plurality of (2N-2) number of electrode pads arranged between the first and second groups of external electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.