DAC calibration
US8134486B2 · kind B2 · utility
15Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2010 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Sep 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/74
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Mechanisms to calibrate a digital to analog converter (DAC) of an SDM (sigma delta modulator) are disclosed. An extra DAC element in addition to the DAC is used to function in place of a DAC element under calibration. A signal (e.g., a random sequence of −1 and +1) is injected to the DAC element under calibration, and the estimated error and compensation are acquired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.