Drive circuit for generating a delay drive signal
US8134525B2 · kind B2 · utility
1Cited by
1References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2007 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Sep 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0223
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A drive circuit includes a drive unit coupling with data lines for receiving at least one clock signal and a first enable signal to generate a drive signal to drive data lines, and a delay unit electrically coupled with the drive unit for receiving the clock signal and the first enable signal and generating a second enable signal falling subsequent to the first enable signal in a predetermined time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.