Source line driving circuit, active matrix type display device and method for driving the same
US8134531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2007 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Jan 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0235
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
If the frequency of a clock signal is increased, the pulse width of a sampling pulse is decreased, and the amount of time for a video signal to be written to a source line is inadequate. Sampling pulses (sam) rise sequentially in synchronization with the rise of a start pulse (SP). As the start pulse (SP) rises, synchronized with the rise of clock signals (CK, CKB), the sampling pulses (sam) fall off sequentially, delayed by half the period of the clock signals (CK, CKB) for every step. As a result, the sampling pulses (sam) with a pulse width longer than one period of the clock signals (CK, CKB) are generated. In a period Ta, a desired video signal (VIDEO) is written to its corresponding source line. In this way, the time for half a period of the clock signal can be secured for writing to the source line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.