Adaptive clock and equalization control systems and methods for data receivers in communications systems
US8135100B2 · kind B2 · utility
17Cited by
2References
20Claims
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Key dates
| Filing date | Aug 20, 2008 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | May 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods for adaptive clock and equalization control are provided for data receivers, which are based on a “closed loop” sampling clock framework that employs controllable and dynamically adapted time offsets on both local data and amplitude clocks. The controllable clock offsets are dynamically adapted using signal processing methods adapted to achieve optimum sampling of data and amplitude sampling clock signals to accurately detect data bits and optimize system equalization settings, including, decision-feedback equalizer and/or an optional linear equalizer preceding a decision-feedback equalizer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.