Circuit for correcting an output clock frequency in a receiving device
US8135105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2008 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Nov 23, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An output clock correction circuit (14) for correcting a frequency of an output clock in a receiving device (13) that receives data (16) and a time stamp component (18) includes an output clock feedback loop (20), a FIFO buffer (22) and a time stamp adjuster (24). The output clock feedback loop (20) adjusts a phase and/or a frequency of the output clock based at least partially on the time stamp component (18). The FIFO buffer (22) temporarily stores the data (16). The time stamp adjuster (24) selectively adjusts the time stamp component (18) based on a status of the FIFO buffer (22). In one embodiment, the status is based at least in part on an actual data level in the FIFO buffer (22). In another embodiment, the FIFO buffer (22) has a target data level range, and the time stamp adjuster (24) adjusts the time stamp component (18) when the actual data level in the FIFO buffer (22) is outside this range. The time stamp adjuster (24) can adjust the time stamp component (18) by an amount that is based on a calculation, or an amount that is determined from a lookup table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.