Multi-mode iterative detector
US8136005B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2007 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Jan 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0065
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A storage system comprises a linear block encoder. A write circuit writes an output of the linear block encoder to a storage medium. A read circuit reads data from the storage medium. A channel decoder decodes the data. A soft linear block code decoder that decodes the data decoded by the channel decoder. The channel decoder decodes the data read in a first iteration. In a subsequent iteration the channel decoder decodes the data read by the read circuit and utilizes information decoded by the soft linear block code decoder. A threshold check circuit selects an output of the soft linear block code decoder if a number of parity check violations has a first relationship with respect to a threshold, or an output of the channel decoder if the number of parity check violations has a second relationship with respect to the threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.