ECC with out of order completion
US8136008B1 · kind B1 · utility
5Cited by
4References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2011 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Apr 19, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4146
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder. The ECC decoder includes one or more stages and at least one of the stages is coupled to a memory configured to store data associated with the at least one stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.