Non-volatile semiconductor memory device
US8136014B2 · kind B2 · utility
10Cited by
10References
10Claims
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Key dates
| Filing date | Sep 24, 2007 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Jul 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5643
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.