Patent · US Active

Optional memory error checking

US8136024B2 · kind B2 · utility

0Cited by

5References

20Claims

0Family size

Assignee

Dell Products L.P. · US

Inventors

Ayedin Nikazm · Austin, US
William Sauber · Georgetown, US

Key dates

Filing date	May 6, 2008
Grant date	Mar 13, 2012
Priority date	—
Expiry date	Jan 12, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory error checking system includes a controller that is operable to transmit memory signals and error check signals. A first memory device coupler is coupled to the controller and operable to couple to a first memory device. The first memory device coupler is operable to transmit the memory signals from the controller to the first memory device. A first error check device coupler is coupled to the contoller and operable to couple to a first error check device that is separate from the first memory device. The first error check device coupler is operable to transmit the error check signals from the controller to the first error check device to be used to error check the memory signals transmitted to the first memory device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.