Standard cell placement
US8136072B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 3, 2008 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Mar 15, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard cells, each standard cell representing a potential component for forming the integrated circuit, providing compatibility information indicative of the compatibility of the boundaries of the standard cells, and generating a placement of standard cells in dependence on the functional data and the compatibility information to produce the layout such that no abutting cells have incompatible boundaries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.