Method for forming laminated structure and method for manufacturing semiconductor device using the method thereof
US8138023B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2006 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Apr 25, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device includes the steps of (a) preparing a wafer including a first circuit formation region and a first surrounding region, (b) laminating a first chip on the first circuit formation region, (c) pouring a first underfill into a first space between the first circuit formation region and the first chip from the first surrounding region, (d) hardening the first underfill, (e) forming a laminated structure comprised of a first chip block that includes a second chip including the first circuit formation region, the first chip, and the first underfill by conducting dicing with respect to the wafer; and (f) laminating the laminated structure on a substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.