Layout structure of MOSFET and layout method thereof
US8138557B2 · kind B2 · utility
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2References
8Claims
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Key dates
| Filing date | Nov 11, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Feb 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout structure of a MOSFET is provided. The layout structure of the MOSFET includes a plurality of MOSFET cells, a first source/drain metal bus structure and a second source/drain metal bus structure. The first source/drain metal bus structure is electrically connected to first sources/drains of the MOSFET cells, and a width thereof is gradually decreased in a predetermined direction. The second source/drain metal bus structure is electrically connected to second sources/drains of the MOSFET cells, and a width thereof is gradually increased in the predetermined direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.